Notes / Section 3
Computer Organization and Architecture
Instruction set and addressing modes
Instruction set and addressing modes.
ALU and control unit design
Design of ALU. Design of control unit: hardwired and microprogrammed.
Memory hierarchy and cache
Memory interfacing and hierarchy: performance, cache memory mapping.
I/O interface: interrupts and DMA
I/O interface (interrupt and DMA).
Instruction pipelining and hazards
Instruction pipelining, pipeline hazards.